AMMTO Semiconductor Workshop 4
Workshop 4
Advanced Packaging for Energy Efficient Microelectronics
January 10-11 & 19-20, 2022
On January 10-11 and 19-20 the AMO hosted it’s fourth workshop as first a widely attended webinar and an invite-only Roundtable. The fourth workshop was entitled: Advanced Packaging for 3D Microelectronics.” The packaging stage in microelectronics fabrication means more today than just the encapsulation or protection of the electronics from the external environment. In “advanced packaging” new techniques are being developed to create complex electronic and structural connections between system subcomponents – often combining different technologies and substrates.
With the end of automatic chip energy efficiency improvements through Moore’s law, use of more advanced packaging will enable continued improvement in computing performance by enabling its functional diversification (i.e., heterogenous integration) and by increasing device density on the package level with 2.5 and 3D approaches. Advanced packaging can also decrease cost and increase energy efficiency by reducing the need for monolithically integrated devices and allowing for mass customization.
As a result, the semiconductor industry is now using advanced packaging techniques to combine multiple advanced node and/or mature chips in a single package. In 2020, advanced packaging represented roughly 44% of the total integrated circuit (IC) packaging market of approximately $60 billion. Semiconductor industry innovations in the design and manufacture of the latest system-on-chips (SoCs) using system-in-package (SiP) and chiplet-based approaches require advanced packaging.
Thus, advanced packaging is forecasted to grow by 58% over the next five years, twice as fast as traditional packaging. The both segments of the fourth workshop the webinar and then the roundtable involved discussions of opportunities and R&D challenges in three critical topics in advanced packaging of 3D microelectronics:
- Thermal management
- I/O and interconnects
- Metrology
The panel on thermal management discussed approaches to better manage heat and reduce thermal stresses, including advanced materials and software modeling tools. The panel on I/O and interconnects discussed key interconnect technologies to route power and signals within and between layers, including through-silicon-vias (TSVs) and co-packaged optics.
The panel on metrology discussed key considerations, techniques, and standards for advanced metrology for 3D devices, including nanoscale electrical, thermal, and mechanical metrology, and through-chip imaging. During the roundtable, a smaller, more expert group of attendees identified challenges and R&D pathways for these three topics.
