Azeez Bhavnagarwala, Ph.D.
Dr Azeez Bhavnagarwala is an expert in CMOS Memories with a career spanning over 2 decades as a Research Scientist in low power SRAM circuits and technology development. He founded Metis Microsystems to develop CMOS Memory and Arithmetic components with industry-leading efficiency and speed for AI hardware.
He served on the Technical Program Committee of the ISSCC [Technology Directions Subcommittee], the VLSI Circuits Symposium and the ICCD. His publications are amongst the top 3 most cited in SRAM and also listed under Top Tech Transfers to industry by the SRC in the 30-year anniversary Review of the SRC. He received the Outstanding Innovation Award from IBM for work done on one of his SRAM patents along with several supplementary patent awards. Some of his SRAM Patents were sold (by IBM) to TSMC, Google, Microsoft & Cypress (now Infineon).
CMOS circuit architectures developed at Metis harvest the energy of on-chip transient data enabling over 2X faster SRAM access and cycle times at less than 20% of the energy consumed by industry-best published arrays. Harvesting circuits also enable 4X lower variance in bit cell signal development time at higher cell stability while eliminating the substantial dissipations from half-selected bitcells during a Read or Write access with benefits directly translating into substantial energy-efficiency and performance advantage over conventional arrays in AI hardware as well as in cryogenic environments. Metis was recognized by EETimes in its ‘100 Silicon Startups to follow’ list and was selected to join the ‘NYSE Wired’ community of AI startups at the New York Stock Exchange.
Azeez received his B.S. in Electrical Engineering [cum laude] from RPI (Troy, NY) and the ETH (Zurich, Switzerland). He received his Ph.D. in Electrical Engineering from the Georgia Institute of Technology with Professor James Meindl as his Thesis Advisor.
